Mixed signal design flow, a mixed signal PLL case study

Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- µ m CMOS process technology

Reconfigurable K-best MIMO detector architecture and FPGA implementation

In a MIMO communication system, K-best decoding algorithm achieves near optimal performance with reduced complexity. Simulation results show that a reconfigurable MIMO detector can improve system performance ove

An overview of reconfigurable VLSI based signal processing building blocks for next generation wireless devices

The introduction of advanced features in mobile communications services requires improvements upon current hardware design and verification methods. The implementation of higher bandwidth features such as streaming video, on-demand video conferencing, etc. dictates that the wireless hardware used in the eventual deployment of next generation (fourth generation or 4G) wireless devices must evolve significantly to provide the expected quality of service (QoS) while minimizing device size and power consumption. This paper outlines the potential digital building blocks of an advanced wireless communication system, incorporating reconfigurable logic principles, suitable for consideration in the development of next generation wireless systems